THURSDAY, MAR26
1. Trezor 5 chip attack, 2. PIPEs for scaling, 3. High throughput, 4. Merchant silicon market
From Proto and Bitkey - part of the Bitcoin ecosystem at Block, Inc.
1. chip
Security researchers have demonstrated a high-success hardware attack against the STM32U5 microcontroller, the chip powering the Trezor Safe 5 bitcoin wallet. According to Denis Laskov in Eye on Cyber, bachelor's thesis researcher Oliver Simonik tested two fault injection techniques against the chip: voltage glitching, which briefly disrupts the power supply, and electromagnetic fault injection, which delivers EM pulses without physical contact. The voltage glitching attack proved remarkably effective, achieving "up to a 76% success rate in bypassing the PIN check." More concerning, the research observed that glitching sometimes caused the chip to output unexpected additional memory data beyond wrong answers, suggesting accidental disclosure of internal memory chunks — a vector that warrants further investigation. The findings matter broadly for the self-custody ecosystem, the STM32U5 is used across multiple open-source hardware wallet designs, meaning the attack surface is not limited to Trezor. As hardware wallets become the default custody layer for serious bitcoin holders, rigorous fault injection research like this is essential infrastructure for the field.
-EDITOR·OP_DAILY2. scaling
Researcher Misha Komarov presented a progress update on Bitcoin PIPEs at the Bitcoin++ Scaling Edition conference, outlining an approach to enable covenants and zero-knowledge proof verification on Bitcoin without a soft fork. Komarov described PIPEs as applying advanced cryptography to achieve "conditional decryption of a key or signature" that attests to the correct off-chain execution of a computation, making the process non-interactive. The construction moves verification work off-chain entirely, allowing ZK rollups to perform pessimistic state transition verification in a single transaction with no optimistic games or interactivity. The current V1 prototype relies on quadratic functional encryption with polynomial attack complexity, an economic security model where attacking a pipe costs far more than the protected value, estimated at roughly one million satoshis per pipe. V2 targets exponential attack cost, matching the security model of Bitcoin private keys. Komarov acknowledged the significant CPU overhead, currently requiring commercially available servers, as the primary friction point. The research remains in active development, with a prospective PipeScript extension set and no launch timeline announced.
-EDITOR·OP_DAILY3. throughput
A developer posting under the handle shrec has introduced UltrafastSecp256k1 to the Delving Bitcoin forum, an open-source high-throughput implementation of the secp256k1 elliptic curve library targeting performance across architectures from x86 servers to ESP32-S3 embedded devices. Open-sourced, the library applies hardware acceleration via SHA-NI and AVX2 instruction sets, GLV endomorphism for scalar multiplication, and a zero-allocation hot-path design that eliminates heap overhead during critical operations. A roughly 59 percent reduction in instruction-cache misses was achieved by applying noinline directives to large functions. The library ships with bindings for more than 12 languages including Rust, Go, Swift, and Dart, and currently passes over 12,000 consistency tests across x86 and ARM64. Shrec is specifically seeking peer review of constant-time integrity, SafeGCD inversion, and branchless signing flows. Faster, more portable secp256k1 implementations matter broadly for Bitcoin wallet software, signing devices, and any application layer that calls cryptographic primitives at volume, making community audit of this work timely.
-EDITOR·OP_DAILY4. merchant
Arm Holdings made a fundamental shift in its business model, announcing its first production silicon product after more than 35 years as a pure IP licensing firm. According to TheEnergyMag, the Arm AGI CPU targets agentic AI infrastructure and is built on a 3nm process using the Neoverse V3 platform, offering up to 136 cores per chip in a dual-chiplet design with support for 6TB of DDR5-8800 memory. CEO Rene Haas stated that "AI has fundamentally redefined how computing is built and deployed," framing the move as expanding partner choices for global-scale agentic AI. Meta served as lead co-developer and plans to pair the chip with its own MTIA accelerators across gigawatt-scale data centers, with OpenAI, Microsoft, Google, and Oracle among early adopters. Arm claims the chip delivers more than twice the performance per rack versus current x86 systems, projecting up to $10 billion in capex savings per gigawatt of data center capacity. For the energy and compute infrastructure sector, the entry of a new merchant CPU vendor targeting the hyperscale market introduces direct pricing pressure on Intel and AMD while potentially reshaping how power-dense AI workloads are provisioned at scale.
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